Houxuan Guo

Houxuan Guo

Northwestern University

About me

I’m a PhD candidate in Computer Engineering at Northwestern University. My researches focus in fault-tolerance hardware design, reconfigurable architectures, on-device learning, and hardware-algorithm co-design.

I focus on building resource-efficient and fault-resilient neural network accelerators and compilation frameworks. My work spans automated ML compilation toolchains, fixed-point on-device backpropagation, post-silicon ASIC bring-up, and hardware reliability for edge computing platforms.

Publications

Conferences

  • Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators
    Houxuan Guo, M. B. Valentín, X. He, and S. Ogrenci
    2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025 | IEEE Xplore

  • ENABOL: Enabling Stable On-Chip Learning via Adaptive Lipschitz Budgeting
    M. B. Valentín, Houxuan Guo, R. Forelli, E. Gindlesperger, and S. Ogrenci
    Design, Automation and Test in Europe (DATE), 2027 (Under Review)

Journals

  • NetSuRF: A Resource-Aware Fault-Tolerant Design Flow for Machine Learning on Edge Devices
    M. B. Valentín, Houxuan Guo, X. He, and S. Ogrenci
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026 (Under Review)

Experience

Fermi National Accelerator Laboratory (Fermilab)

Visiting Researcher | Batavia, IL
Jul. 2023 – Present

  • ML Accelerator Co-Design: Validated Cryo-AI ASIC for sub-millisecond edge neural network inference; executed post-silicon functional bring-up of core logic and high-speed I/O channels.
  • ML Compiler & Framework Integration: Integrated hls4ml neural network compiler with the ESP SoC platform to automate mapping and fixed-point quantization of PyTorch/ONNX models into custom hardware accelerators.
  • High-Throughput Data Interface: Built streaming data verification testbenches for photonic mixed-signal blocks, optimizing data conversion throughput and signal integrity.

Education

  • Northwestern University Ph.D. Candidate in Computer Engineering (Present)
  • Northwestern University M.S. in Electrical Engineering (2023)
  • University of Shanghai for Science and Technology B.E. in Electrical Engineering (2022)

Skills

  • Machine Learning & Systems: PyTorch, ONNX, Quantization-Aware Training (QAT), Pruning, On-Device Learning, hls4ml, Keras/TensorFlow, Model Compression
  • Languages & Scripting: Python (NumPy, SciPy), C/C++, SystemVerilog, Verilog, CUDA, MATLAB, Bash, Tcl, Git, Linux
  • Hardware Architecture: Edge AI Accelerators, FPGA (Vivado, Vitis), High-Level Synthesis (HLS), Fixed-Point Arithmetic, ASIC/SoC Co-Design, UVM, ESP SoC Platform
  • EDA Tools: Cadence (Genus, Innovus, Xcelium, Virtuoso), Synopsys (Design Compiler, VCS), Siemens Questa